Patent US 5,737,564

A cache memory system includes a plurality of processors and a plurality of caches respectively assigned to the plurality of processors. Each cache is mapped to a different region of the main memory, so that memory contention is lessened to a great extent. Based on a memory address received by a cache, the cache compares the memory address to its assigned region of addresses. If the memory address falls within the assigned region for the cache, the cache then examines its contents as to determine if there is an address hit in the cache. If the memory address does not fall within the assigned region for the cache, the cache does not examine its contents to determine if there is an address hit in the cache, since an address hit is not possible in that case.