Patent US 5,481,485

In a device simulation apparatus, the structural parameters of a single sample field effect transistor are retrieved from a memory and a set of voltage parameters is established. A source-drain current value and a potential distribution are derived from the structural parameters. A source-drain resistance value is then derived from the source-drain current value and one of the voltage parameters and a channel resistivity value is derived from the potential distribution and the source-drain current value. One of the voltage parameters is successively updated to repeat the process on the updated parameter to produce a said plurality of source-drain current values and a plurality of channel resistivity values. The effective channel length of the transistor is determined from the source-drain resistance values and the channel resistivity values.