Patent US 5,481,469

A method for automatic power vector generation for sequential circuits produces input vectors for a power simulation required for accurate calculation of power dissipation of logic elements. More particularly, a worst-case-power-consumption logic vector pair for a sequential circuit is automatically generated by determining the worst-case-power-consumption logic vector pair, the second worst-case-power-consumption logic vector pair, up to the Nth worst-case-power-consumption logic vector pair in the combinational logic portion of the sequential circuit. The following is determined with respect to each of the N vector pairs: whether a feedback portion of a second logic vector in the logic vector pair is consistent with a feedback portion of a first logic vector output signal of the sequential circuit produced in response to a first logic vector in the logic vector pair, signifying that the second logic vector can be produced from the first logic vector; and, a setup vector sequence, for the first logic vector, of one or more logic vectors that when applied to the sequential circuit causes the feedback portion of the first logic vector to be produced, if such a setup sequence can be found. This procedure continues until for a particular logic vector pair the second logic vector can be produced from the first logic vector, and a setup sequence for the first logic vector has been found. The particular logic vector pair is then the worst-case-power-consumption logic vector pair. The worst-case-power-consumption logic vector pair and corresponding set-up vector sequence can then be used with a power simulation to find worst-case-power-consumption of the sequential circuit.