Patent US 5,509,130

In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n.sub.1 and n.sub.2 integer and floating point results per clock cycle respectively, where n.sub.1 and n.sub.2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache. The instruction control unit decodes the instructions, detects operands cascading from instruction to instruction, group instructions into instruction groups of at most m instructions applying a number of exclusion rules, and issuing the grouped instructions simultaneously to the integer and/or floating point unit for execution. The exclusion rules reflect the resource characteristics and the particular implementation of the pipelined processor. The instruction control unit also tracks the history of the instruction groups and uses the history in conjunction with the exclusion rules in forming the instruction groups.