REDUNDANT LOAD ELIMINATION ON OPTIMIZING COMPILERS

Patent №

US 5,537,620

Granted

1996-07-16

Filed 1994

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

08307216

A method for eliminating redundant loads in an optimizing compiler is provided. When a LOAD and memory operation occur in an iterative loop structure having an induction variable, the method determines if redundant load elimination optimization may be performed by performing the steps of: creating a symbolic address for a LOAD operation, where the LOAD operation follows a memory operation, creating a symbolic address for the memory operation which precedes the LOAD, and subtracting the LOAD symbolic address from the memory operation symbolic address to generate a difference. If the difference is a constant which is divisible by the increment of the induction variable, the method eliminates the LOAD instruction for each increment of the loop and includes an instruction to copy the value of the memory operation to a register, and further includes an instruction to move the copied value from the register to the target of the load. An additional feature of the invention includes the step of, if the difference is a constant which is divisible by a multiple of the increment of the induction variable, wherein the multiple is greater than one, including additional instructions to copy the value of the memory operation to a separate register for each iteration during a number of iterations equal to the multiple.

AI classification

AI hardware0.81
Evolutionary computation0.05
Natural language0.02
Vision0.01
Knowledge representation0.01
Planning0.00
Speech0.00
Machine learning0.00

Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 71610742

Assignors

BRETERNITZ, MAURICIO, JR.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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