CIRCUIT AND METHOD FOR SCHEDULING INSTRUCTIONS BY PREDICTING FUTURE AVAILABILITY OF RESOURCES REQUIRED FOR EXECUTION
Patent №
US 5,555,432
Granted
1996-09-10
Filed 1994
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08293388
An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.
AI classification
Ownership
INTEL CORPORATION
assignment · 72920865
Assignors
HINTON, GLENN J., MARTELL, ROBERT W., FETTERMAN, MICHAEL A., PAPWORTH, DAVID B., SCHWARTZ, JAMES L.
On an employer assignment, the assignors are typically the inventors.