PARAMETERIZED GENERIC MULTIPLIER COMPLIER

Patent №

US 5,566,079

Granted

1996-10-15

Filed 1992

Owner

Lab

AI components

2

planning · hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

07974457

A method for producing a circuit layout comprising the steps of establishing high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path, inputting the input parameters to a compiler, the compiler performing steps of creating a data path netlist by selecting data path components in response to the established high-level input parameters; and automatically selecting control logic for the data path components. The data path netlist is a high-level netlist of Boolean logic which can then easily be translated into a gate level implementation of the circuit layout.

AI classification

AI hardware0.99
Planning0.92
Knowledge representation0.14
Natural language0.00
Vision0.00
Evolutionary computation0.00
Speech0.00
Machine learning0.00
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