Patent №
US 5,566,079
Granted
1996-10-15
Filed 1992
Owner
—
Lab
—
AI components
2
planning · hardware
Assignment
None on record
Dataset
AIPD
2023_r1 edition
Application
07974457
A method for producing a circuit layout comprising the steps of establishing high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path, inputting the input parameters to a compiler, the compiler performing steps of creating a data path netlist by selecting data path components in response to the established high-level input parameters; and automatically selecting control logic for the data path components. The data path netlist is a high-level netlist of Boolean logic which can then easily be translated into a gate level implementation of the circuit layout.