METHOD AND SYSTEM FOR CREATING AND VERIFYING STRUCTURAL LOGIC MODEL OF ELECTRONIC DESIGN FROM BEHAVIORAL DESCRIPTION, INCLUDING GENERATION OF LOGIC AND TIMING MODELS

An automatic logic-model generation system operates on a behavioral description of an electronic design (e.g., a circuit, a system, etc.) to automatically generate a low-level (i.e., circuit-level) design of the electronic design, to lay out the electronic design for production in the form of an integrated circuit, and to produce logic-level models incorporating accurate timing (and delay) information. A verification process is also performed whereby the logic-level model is automatically verified for accuracy.