Patent US 5,603,035

A programmable interrupt controller connected to a microprocessor has a register for storing a prevailing vector which is the highest priority vector in service in the microprocessor system. When the microprocessor is executing an interrupt routine, if the programmable interrupt controller or a second programmable interrupt controller connected to the microprocessor receives an interrupt request higher in priority than the executing interrupt, the microprocessor writes the higher priority interrupt vector into the register for storing the prevailing vector of all connected interrupt controllers. Once the higher priority interrupt routine has finished executing, the microprocessor then writes the lower priority previously executing interrupt vector into the register of the prevailing vector of all interrupt controllers and the previously executing interrupt routine continues executing in the microprocessor. The structure of the interrupt controller allows a plurality of interrupt controllers to be connected to the microprocessor without having one of the controllers act as a master and the others as slaves. The order of the priorities of the interrupts for each controller can be programmed using software.