MULTI-WAY SET ASSOCIATIVE CACHE SYSTEM IN WHICH THE NUMBER OF LINES PER SET DIFFERS AND LOADING DEPENDS ON ACCESS FREQUENCY
Patent №
US 5,651,135
Granted
1997-07-22
Filed 1995
Owner
KABUSHIKI KAISHA TOSHIBA
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08413010
A set associative cache system in a computer system having a lower memory is provided with a plurality of cache memory sets. A cache data memory contains a plurality of cache lines to store data in units of blocks corresponding to data stored in the lower memory. A cache tag memory stores lower memory addresses for data stored in the cache lines. The plurality of cache memory sets have different numbers of cache lines. A read/write section reads out data stored in the lower memory into the plurality of cache lines and writing data in the plurality of cache lines back to the lower memory.
AI classification
Ownership
KABUSHIKI KAISHA TOSHIBA
assignment · 74360372
Assignors
HATAKEYAMA, TETSUO
On an employer assignment, the assignors are typically the inventors.