METHOD AND APPARATUS FOR PERFORMING READS OF RELATED DATA FROM A SET-ASSOCIATIVE CACHE MEMORY

Patent №

US 5,802,602

Granted

1998-09-01

Filed 1997

Owner

INTEL CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

08785199

Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the corresponding entries in each of the ways to the related data units, so that related data units are stored in a common set of entries. Accordingly, the related data units will be simultaneously outputted from the set-associative cache memory, and are thus concurrently available for processing. The invention may find application in allocating entries of a common set in a branch prediction table (BPT) to branch prediction information for related branch instructions.

AI hardwareG06F 9/3806G06F 12/0864

AI classification

AI hardware0.84
Planning0.06
Vision0.01
Knowledge representation0.00
Natural language0.00
Machine learning0.00
Evolutionary computation0.00
Speech0.00

Ownership

INTEL CORPORATION

assignment · 84030949

Assignors

RAHMAN, MONIS, POPLINGHER, MIRCEA, YEH, TSE-YU, CHEN, WENLIANG

On an employer assignment, the assignors are typically the inventors.

From the same owner

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