OPERATION UNIT WITH PLURAL OPERATION CIRCUITS HAVING PLURAL DATA BUSES PROVIDING PLURAL OPERATION MODES

An operation unit has operation circuits (aL, aH), temporary registers (xL, yL, xH, yH) arranged just before the operation circuits, registers (R1, R2, R3, R4) arranged if required, and data buses (d1L, d2L, d1H, d2H) for transferring data among the operation circuits, temporary registers, and registers. Data to be processed are divided, are transferred to the operation circuits through the data buses, and are simultaneously and independently processed by the operation circuits. When a result of the preceding operation affects the following operation, data except the result of the preceding operation are transferred from the registers to the temporary registers before starting the operations. These techniques shorten a processing time.