IC CHIPS INCLUDING ALUS AND IDENTICAL REGISTER FILES WHEREBY A NUMBER OF ALUS DIRECTLY AND CONCURRENTLY WRITE RESULTS TO EVERY REGISTER FILE PER CYCLE

A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file located on the ALU chip. Data written by one ALU is "broadcast" to all the "local" register files. This arrangement of "local" register files minimizes the number of pins required and, using very large scale integration (VLSI) techniques, high densities can be achieved. These "local" register files eliminate off-chip delays, and performance is further enhanced by the shorter wire lengths in the local register files.