INSTRUCTION BREAKPOINT DETECTION APPARATUS FOR USE IN AN OUT-OF-ORDER MICROPROCESSOR

Code breakpoint detection logic for a superscalar microprocessor. Superscalar operation in a microprocessor is maintained with a single breakpoint detection mechanism which performs breakpoint detection prior to instruction decoding. One bit for each byte in an instruction packet is provided as a result of a comparison of the aligned instruction fetch to the debug registers. After decoding, if the first byte of an instruction has an appended breakpoint true bit, then an event is signaled for breakpoint handling by the superscalar microprocessor.