BUS CONTROL DEVICE FOR COMPUTER SYSTEM HAVING COMPUTER AND DMA DEVICE

In a bus control device for DMA processing/external master transfer which is carried out by a personal computer having a write back cache, a route having a high-speed buffer inserted between a data bus for peripherals and a host data bus is separately provided, data which are written back (copied) into a main memory through a write-back operation which is required when a cache memory is dirty-hit at a read-access time of a DMA device into a cache area of the main memory are also supplied to and stored in the high-speed buffer as well as the main memory, and the high-speed buffer is allowed to perform a data access with the DMA device or an external bus master. Therefore, the DMA device/external bus master are separated from the host data bus.