PROCESS FOR INTERFACING A MICROPROCESSOR WITH A PACKET BASED DEVICE AND RESPECTIVE SYSTEM

In order to enable interfacing of a microprocessor (1) with a peripheral (3) consisting of a device operating according to high-speed communication specifications (for example, IEEE 1394), it is envisaged that the interface (4) should contain a dedicated memory (40) designed to smooth the delays in communication between the main memory (2) and the peripheral (3). The memory (40) has a trigger (10) that is programmable via software to start a communication when a fraction of the memory (40) or the entire memory (40) is full. When a multiple packet starts to be transferred, a signal is generated to alert the microprocessor (1) of the fact that a transfer is almost completed.