DIGITAL LOGIC SIMULATION/EMULATION SYSTEM

A digital logic simulation/emulation system, that includes a hardware pod having a configurable-logic IC arranged to provide a plurality of stimulus/response cells, is adapted for coupling to a digital logic circuit. The stimulus/response cells, which provide stimulus signals to the digital logic circuit, connect to form a shift-register for downloading stimulus-control data, and for uploading response data during a stimulation-response cycle. A logic-configuration library stores configuration-data for establishing a bit-slice architecture for the stimulus/response cells. To facilitate preparing the configuration-data, the system also includes a configurable-logic-specification process having a GUI user interface. The logic-specification process assigns pre-established, bit-slice configuration data for each logic-function cell to specific locations throughout a configurable-logic IC to achieve swift compilation of configuration data.