DATA PROCESSOR SYSTEM FOR PRELOADING/POSTSTORING DATA ARRAYS PROCESSED BY PLURAL PROCESSORS IN A SHARING MANNER

Patent №

US 5,754,876

Granted

1998-05-19

Filed 1995

Owner

HITACHI, LTD.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

08576131

Preload register groups are respectively provided for the plurality of scalar processors which execute iterative processing in distributed manner. Each group consists of preload registers corresponding to a plurality of data arrays that appear in the iterative processing. According to address information about the plurality of arrays to be preloaded specified by any of the processors, a preload control unit reads partial data groups of one of the arrays to be first processed by all of the processors from the main storage in parallel. Then, the same operation is performed on another array. Subsequently, in the above-mentioned manner, remaining elements of the arrays are read from one array to another. A partial element group thus read sequentially is stored in the plurality of preload register groups in distributed manner. According to a load request issued from each processor, the array elements preloaded in the preload register groups corresponding to that processor are read in the order the array elements were preloaded.

AI hardwareG06F 9/30043G06F 9/30101G06F 9/3455G06F 9/383G06F 15/8092

AI classification

AI hardware0.72
Knowledge representation0.02
Natural language0.00
Vision0.00
Evolutionary computation0.00
Machine learning0.00
Planning0.00
Speech0.00

Ownership

HITACHI, LTD.

assignment · 87980541

Assignors

TAMAKI, YOSHIKO, TANAKA, TERUO, SAKAKIBARA, TADAYUKI

On an employer assignment, the assignors are typically the inventors.

© 2026 NYSGPT2525 LLC