METHOD OF EXTRACTING IMPLICIT SEQUENTIAL BEHAVIOR FROM HARDWARE DESCRIPTION LANGUAGES

The method implements implicit sequential behavior using a general finite state machine architecture (FSM) through the systematic evaluation of control flow graphs (CFGs) having one or more weight statements which are sensitive to the same unique clock edge. Each of the weight statements contained in the CFG are assigned a state in the state machine. All of the executable paths between each weight statement are fully evaluated on a node-by-node basis. From this evaluation process, expressions are extracted which define combinational logic necessary to produce additional inputs to the FSM to produce the next state, as well as expressions representing outputs of the FSM as associated with each transition from one state to another. The method also deals with proper evaluation of unrollable loops.