METHOD AND APPARATUS FOR DISABLING INTERRUPTS IN A HIGHLY PIPELINED PROCESSOR

A method and apparatus disables and re-enables an interrupt during the execution of certain I/O and memory operations in an out-of-order processor. The out-of-order processor executes macroinstructions, wherein each macroinstruction comprises one or more microinstructions. The out-of-order processor comprises a fetch and issue unit and a reorder buffer that allows an interrupt to be serviced during the execution of the microinstructions making up any of a first class of macroinstructions. The reorder buffer, however, does not allow the interrupt to be serviced during execution of microinstructions making up a second class of macroinstructions. The second class of macroinstructions may include I/O and memory operations.