APPARATUS AND METHOD FOR MANAGEMENT OF INTEGRATED CIRCUIT LAYOUT VERIFICATION PROCESSES

An apparatus and method for managing data obtained during the Design Rule Check (DRC) and Layout versus Schematic (LVS) verification procedures executed during the design of an integrated circuit. The apparatus is a data processing system which includes a database containing information regarding the schematics and layouts of the cells of an integrated circuit. The system accesses the database upon the completion of a DRC or LVS operation and queries the user as to whether the cell should be marked as successfully passing the appropriate verification procedure. A user is also able to access a report generating module to inspect the verification status of a cell in the IC design and generate a report showing the status of the verification procedures for each cell, organized according to one of several criteria.