MULTI-PROCESSOR CACHE COHERENCY PROTOCOL ALLOWING ASYNCHRONOUS MODIFICATION OF CACHE DATA

An improved cache coherency protocol is set forth that assures that a collection of processors in a multi-cache system configuration do not disagree about the precedence ordering of store operations that can originate from any and all processors within the system. The protocol maintains coherency while allowing lines to be modified by one processor while other processors access a prior unmodified copy of the line. The benefit of such a system is that line modification need not be done only for lines that are exclusive within the cache that is associated with the modifying processor. The manner in which this coherency is achieved is through the use of line status register which maintains the status of every line in the system and a processor modification register which maintains the identity of all processors that have been granted permission to modify a line that is shared with other processors. The exclusion of the situations where the granting of modify status to a shared line which might create the opportunity for a precedence cycle to materialize is the central aspect of the invention.