PROGRAMMING ARCHITECTURE FOR A PROGRAMMABLE INTEGRATED CIRCUIT EMPLOYING ANTIFUSES

A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. In one aspect, the number of programming conductors and the number of perpendicular programming control conductors for a logic module are substantially equal. In another aspect, programming current is supplied onto long routing wire segments via two programming transistors and two programming conductors. In another aspect, a pattern of programming drivers alternates from one side of the integrated circuit to the opposite side from one column of macrocells to the next. In other aspects, control conductors and programming conductors are tested with test antifuses and test transistors. In another aspect, adjacent logic modules have mirrored structures so that they can share an intervening programming conductor resource. In another aspect, L-shaped programming power busses are provided and in another aspect, an express wire is simultaneously driven with programming current from two different programming voltage terminals. In other aspects, a test circuit tests the integrity of collinear routing wire segments and output programming transistors are tested. In another aspect, antifuses on branches of clock conductors are programmed.