TEST-MODE CONTROL FOR DYNAMIC LOGIC GATES

A dynamic logic circuit having additional test circuitry and control, enabling the dynamic logic gate to operate normally during testing or alternatively to force the dynamic logic gate output to a known state during testing to provide a known input for downstream logic. With the additional test circuitry, there is no need for input test signal sequences to propagate logical test vectors to tested nodes. The dynamic logic circuit includes a storage node that is precharged during a precharge cycle and logic circuitry that may discharge the storage node during an evaluation cycle, depending on logic inputs. The logic circuitry discharges through a clock transistor. Additional test circuitry is added to discharge the storage node during the evaluation cycle, in response to a test control signal and a test state signal. When the dynamic logic gate is operating normally during testing, the test circuitry is disabled. When the gate output is to forced into a known state, the clock transistor is disabled, disabling the logic circuitry, and the test circuitry discharges the storage node, depending on the test state signal.