LATCHED TIME BORROWING DOMINO CIRCUIT

A time borrowing domino circuit that includes complementary logic outputs and a multiplexor without incurring the time delays normally associated with complementary outputs and multiplexor function is described. A clock delay circuit is described which produces the trailing edge delay clock signal that drives the domino circuit. A domino circuit is described that may implement logical functions such as AND, OR, NAND, NOR, EXCLUSIVE-OR and EXCLUSIVE-NOR. A multiplexor circuit is described for gating one of a number of logical inputs to a latch. And a latch is described having complementary outputs.