INSTRUCTION CLASSIFICATION CIRCUIT CONFIGURED TO CLASSIFY INSTRUCTIONS INTO A PLURALITY OF INSTRUCTION TYPES PRIOR TO DECODING SAID INSTRUCTIONS

An instruction classification circuit is provided which speculatively classifies potential instructions prior to the decode of these instructions. In parallel, predecode information associated with the plurality of instruction bytes is scanned to determine the valid instructions within the instruction bytes. Instruction classifications are then chosen from the speculatively generated classifications according to the valid instructions located. Instruction information may be determined prior to decoding the instructions. In one embodiment, instructions are classified as either single dispatch instructions or double dispatch instructions. A single dispatch instruction is dispatched to a single decode unit, while a double dispatch instruction is dispatched to a pair of decode units. Instructions utilizing a pair of decode units are detected prior to dispatch to decode units. Bussing between decode units included when double dispatch instructions are detected within the decode unit may be eliminated. Pipeline stalls created when instructions which were previously dispatched are redispatched due to the detection of double dispatch instructions at the decode stage may be eliminated.