LOW MASK COUNT SELF-ALIGNED SILICIDED CMOS TRANSISTORS WITH A HIGH ELECTROSTATIC DISCHARGE RESISTANCE

A method to fabricate simultaneously a CMOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The NMOS transistor and PMOS transistor in the portion of the CMOS transistor have both anti-punchthrough and salicide structures and individually with n-LDD and p-LDD structure, respectively. The structure of ESD protective devices is fabricated with self-aligned silicide but without LDD, thus the degradation of ESD protection can be solved. The problems of accumulative aberration in scaled devices can also be alleviated through using blanket ion implantation technology and salicide process to reduce the mask count as shown in the invention.