MEMORY DEVICE COMMUNICATION LINE CONTROL

A memory device is described which equilibrates and precharges the input/output lines synchronously during a write cycle and asynchronously during a read cycle. During a read cycle, the timing of equilibration and precharge functions are decoupled from the clock signal and asynchronously initiate the equilibrate and precharge functions of the I/O lines in response to a latch signal. The invention initiates the equilibration and precharging of the I/O lines earlier in the access cycle thereby increasing memory access speed.