CASCADABLE MULTI-CHANNEL NETWORK MEMORY WITH DYNAMIC ALLOCATION

A memory array comprising a plurality of storage elements and a logic circuit. The memory array may be configured to (i) receive a plurality of input data streams, (ii) store each of the plurality of input data streams in one or more of the storage elements in response to a plurality of control signals and (iii) present a plurality of output data streams in response to the plurality of input data streams. The logic circuit may present the plurality of control signals in response to the fullness of each of the plurality of storage elements.