METHOD TO PARTITION CLOCK SINKS INTO NETS

A method of designing the clocking circuitry of an integrated circuit chip. The load sinks are assigned to clock nets, each clock net having less then a maximum load. The first step is selecting a pair of clock nets for improvement. Next, a subset of the load sinks of the pair of clock nets are assigned to each clock net. Thereafter, the unassigned load sinks are assigned in all possible combinations to each of the pair of clock nets. A penalty function for each load sink assignment, and the assignment having the best penalty function is kept.