REAL TIME QUIESCENT CURRENT TEST LIMIT METHODOLOGY

Patent №

US 6,013,533

Granted

2000-01-11

Filed 1997

Owner

LSI LOGIC CORORATION

Lab

AI components

1

planning

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

08924187

A method of sorting dies found on wafers is disclosed. Each wafer is part of a set of wafers and the sorting rejects some of the dies. The method first selects an acceptable deviation within an abstract distribution. A respective test parameter is measured and recorded for each die in the set of wafers, and a distribution of the test parameter across the set of wafers is calculated. Based on this distribution and the acceptable deviation, a test parameter limit is set and any dies having a test parameter value greater than the limit are rejected.

PlanningG01R 31/3004G01R 31/01G01R 31/2831

AI classification

Planning0.86
Machine learning0.10
Evolutionary computation0.02
Knowledge representation0.01
AI hardware0.01
Vision0.00
Natural language0.00
Speech0.00

Ownership

LSI LOGIC CORORATION

assignment · 87020534

Assignors

SUGASAWARA, EMERY OSAMU, KELLER, SCOTT FRANKLIN

On an employer assignment, the assignors are typically the inventors.

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