CORE-BASED PLACEMENT AND ANNEALING METHODS FOR PROGRAMMABLE LOGIC DEVICES

A core-based PLD programming method for programming a PLD to implement a user-defined logic operation including a set of cores. The PLD includes several configurable logic blocks (CLBs). Each core includes several logic portions that are arranged in a fixed pattern, and each logic portion includes configuration data for configuring one CLB. A placement process is performed during which only a single reference logic portion of each core is placed in a configuration data table to form a first placement pattern. Non-reference portions of the cores are not placed in the configuration data table during the initial placement process. An annealing process is then performed during which the reference logic portions associated with the cores are moved between CLB sites in an attempt to identify an optimal placement solution. A separate CLB site overlap table is utilized to keep track of the non-reference logic portions during the annealing process. The CLB site overlap table includes memory locations that are assigned to each CLB site. Each memory location stores an integer value indicating the number of reference logic portions and non-reference logic portions assigned to an associated CLB site. A cost value that is based on the placement arrangement and overlap information is utilized by an annealing engine to "drive" the annealing process toward an optimal placement solution. After an optimal placement solution is found, the non-reference logic portions of the cores are placed.