METHOD AND APPARATUS FOR PERFORMING RETIMING ON FIELD PROGRAMMABLE GATE ARRAYS

Patent №

US 7,360,190

Granted

2008-04-15

Filed 2004

Owner

ALTERA CORPORATION

Lab

—

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10876709

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A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.

AI hardwareG06F 30/392G06F 30/398

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AI hardware0.64

Machine learning0.30

Planning0.04

Knowledge representation0.02

Natural language0.00

Evolutionary computation0.00

Speech0.00

Vision0.00

Ownership

ALTERA CORPORATION

assignment · 155320172

Assignors

SINGH, DESHANAND, QUAN, GABRIEL, BORER, TERRY, CHESAL, IAN, MANOHARARAJAH, VALAVAN, SCHABAS, KARL, BROWN, STEPHEN

On an employer assignment, the assignors are typically the inventors.

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Cites (2)

METHOD AND APPARATUS FOR DEVELOPING AND PLACING A CIRCUIT DESIGNUS 6,631,508 · 2003 CORE-BASED PLACEMENT AND ANNEALING METHODS FOR PROGRAMMABLE LOGIC DEVICESUS 6,099,583 · 2000

Cited by (10)

METHODS FOR INCREMENTAL CIRCUIT DESIGN LEGALIZATION DURING PHYSICAL SYNTHESISUS 10,339,241 · 2019 OVERCOMING RETIMING LIMITATIONS DUE TO INITIAL CONDITIONS CONFLICTSUS 10,282,508 · 2019 INTEGRATED CIRCUIT RETIMING WITH SELECTIVE MODELING OF FLIP-FLOP SECONDARY SIGNALSUS 10,162,918 · 2018 METHOD AND APPARATUS FOR PERFORMING REGISTER RETIMING IN THE PRESENCE OF TIMING ANALYSIS EXCEPTIONSUS 9,710,591 · 2017 METHODS AND TOOLS FOR DESIGNING INTEGRATED CIRCUITS WITH AUTO-PIPELINING CAPABILITIESUS 9,251,300 · 2016 BOUNDARY BUFFERS TO MODEL REGISTER INCOMPATIBILITY DURING PRE-RETIMING OPTIMIZATIONUS 8,423,939 · 2013 METHOD AND APPARATUS TO OPTIMIZE ADAPTIVE RADIO-FREQUENCY SYSTEMSUS 8,136,081 · 2012 TIMING DRIVEN LOGIC BLOCK CONFIGURATIONUS 7,926,016 · 2011 Patent US 10,339,238US 10,339,238 Patent US 10,949,599US 10,949,599

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