SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device can include a synchronous dynamic random access memory array and a register array formed from static random access memory cells. The memory device can be used in image processing, and reduce the time for data reads and writes during image reset operations. One embodiment (100) can include a memory cell array (102) having a number of memory cells arranged in rows and columns, and a register array (104) that includes a number of channel registers (106-11 to 106-mn) arranged rows and columns that correspond to at least a portion of the memory cell array rows and columns. The memory cells of a first column and the registers of a corresponding column are connected to one another by data transfer buses (108-1T/108-1N to 108-mT/108-mN). Data values can be written to memory cells and corresponding channel registers (106-11 to 106-mn) at the same time. Alternatively, data can be transferred between memory cells and corresponding channel registers (106-11 to 106-mn).