METHODS AND APPARATUSES FOR AUTOMATIC EXTRACTION OF FINITE STATE MACHINES

A method and apparatus which automatically extract finite state machine circuits from a circuit design. Typically, the circuit design is specified by a hardware description language which is compiled to a level of description which shows logic and interconnections in the circuit. A circuit region which includes a register is automatically defined from this description. The circuit region is defined as the register and the group of logic gates within a feedback path from the output of the register to the input of the register. The circuit region is analyzed to define a finite state machine. For each finite state machine, the next state function of the state machine is determined. The next state function is derived by determining a next state from a current state of the state machine and a set of possible input values to the state machine. A symbolic representation of the state machine may be generated from the next state function, and state machine may be optimized and/or debugged in its symbolic representation. The state machine may then be recompiled from the symbolic representation. In one example, the state machine may be recompiled into a target architecture.