Patent №
US 6,188,974
Granted
2001-02-13
Filed 1998
Owner
IBM CORPORATION
Lab
AI components
2
planning · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09046229
A method comprising a computational procedure for obtaining reduced-order models of partial element equivalent circuit (PEEC) models of very large scale integrated (VLSI) interconnects. The methodology is not limited to PEEC applications, and can be used for generating reduced-order models of other systems which can be modeled with linear, time-invariant systems of ordinary differential equations with time delays.
AI classification
AI hardware0.98
Planning0.90
Machine learning0.45
Evolutionary computation0.02
Speech0.00
Vision0.00
Natural language0.00
Knowledge representation0.00
Ownership
IBM CORPORATION
assignment · 92040429
Assignors
CULLUM, JANE G.K., RUEHLI, ALBERT E.
On an employer assignment, the assignors are typically the inventors.
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