DESIGN LEVEL OPTICAL PROXIMITY CORRECTION METHODS

A method for integrating correction features onto selected design features of an integrated circuit mask. The method includes identifying a minimum dimension in the integrated circuit mask. The minimum dimension is configured to define transistor gate electrode features or any critical feature geometry. The method then includes removing feature geometries that are dimensionally larger than the minimum dimension. After the removing operation, correction features are integrated with selected ends of the transistor electrode features that have the minimum dimension to produce corrected transistor gate electrode features. Then, the method includes the operation of adding the corrected transistor gate electrode features to the removed feature geometries that are dimensionally larger than the minimum dimension to produce a corrected integrated circuit mask.