METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR GENERATION OF A VIA ARRAY WITHIN A FILL AREA OF A DESIGN LAYOUT
Patent №
US 7,007,258
Granted
2006-02-28
Filed 2003
Owner
SUN MICROSYSTEMS INC.
Lab
—
AI components
1
vision
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10461041
A technique for generating via array is presented. An origin is set in one corner of a bounding box, and the bounding box is filled, according to at least one spacing rule, starting from the origin, with one or more vias. The bounding box can be defined using a width and a length wherein the bounding box is at least co-extensive with an area for via filling. The bounding box can be larger than the area to be filled, for example, to allow for a metal enclosure or to allow for a non-rectangular area such as a polygon to be filled. When the area to be filled is a polygon, a bounding box of the polygon is filled with vias, any vias outside the polygon can be removed, and any vias crossing a polygon edge can be resized or removed.
AI classification
Ownership
SUN MICROSYSTEMS INC.
assignment · 141740978
Assignors
LI, MU-JING
On an employer assignment, the assignors are typically the inventors.