APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION IN A DATA PROCESSOR EXECUTING AN APPLICATION CODE

Apparatus and methods are described for reducing power consumption in a processor. The processor includes a source of microcode instructions, a microcode instruction decode circuit, control register latches and a clock gate control circuit that is coupled to the source of microcode instructions. The clock gate control circuit searches and picks groups of clock gate control signals for the latches that are the same value (state) as control signals form a previous cycle. The clock gate control circuit includes a table, a table lookup circuit, a storage circuit, a compare circuit and a latch prevent circuit