MULTIPROCESSOR ARCHITECTURE OPERATION

The present invention discloses a method of controlling the interaction of a host CPU (202) and at least one co-processor (224) in a computer system (201) to permit substantially simultaneous decoupled execution of CPU instructions and co-processor instructions. The co-processor instructions to be executed, and those which have been executed are allocated to respective queues (1040, 1041). From time to time the latter queue (1041) is cleaned up under control of the CPU (202) to release memory resources previously allocated to the co-processor by the CPU. This dynamic memory management arrangement preferably includes an instruction generator (1030), a memory manager (1031) and a queue manager (1032).