A METHOD FOR FORMING HIGH DENSITY FLASH MENORY

A method of forming a memory array. The method includes forming a plurality of first conductivity type semiconductor pillars upon a substrate. Each pillar has a top and a side surface. The method includes forming a plurality of first source/drain regions, of a second conductivity type. Each of the first source/drain regions formed proximally to an interface between the pillar and the substrate. The method includes forming a plurality of second source/drain regions, of a second conductivity type, each of the second source/drain regions formed within one of the pillars and distal to the substrate and separate from the first/source drain region. A gate dielectric is formed on at least a portion of the side surface of the pillars. At least two floating gates are formed per pillar. Each of the floating gates are formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric, a plurality of control gates are formed substantially adjacent to at least one of the floating gates and insulated therefrom. An intergate dielectric is formed, interposed between ones of the floating gates and ones of the control gates. A plurality of first gate lines are formed such that each first gate line interconnects ones of the control gates. The method includes forming a plurality of second gate lines, each second gate line interconnecting ones of the control gates. At least one first source/drain interconnection line is formed interconnecting ones of the first source/drain regions. And, the method includes forming a plurality of data lines such that each data line interconnects ones of the second/source drain regions.