METHOD AND APPARATUS FOR DYNAMIC PARTITIONABLE SATURATING ADDER/SUBTRACTOR

Patent №

US 6,301,600

Granted

2001-10-09

Filed 1998

Owner

EVSX, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09195752

An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.

AI hardwareG06F 7/503G06F 7/5016G06F 2207/382G06F 2207/3828G06F 2207/3872

AI classification

AI hardware0.96
Machine learning0.02
Vision0.01
Natural language0.01
Knowledge representation0.00
Evolutionary computation0.00
Speech0.00
Planning0.00

Ownership

EVSX, INC.

assignment · 96080973

Assignors

PETRO, ANTHONY M., BLOMGREN, JAMES S.

On an employer assignment, the assignors are typically the inventors.

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