ON-CHIP TESTING CIRCUIT AND METHOD FOR IMPROVING TESTING OF INTEGRATED CIRCUITS

An on-chip test circuit in an integrated circuit includes a comparison circuit and a fail data register. An output of the comparison circuit is coupled to an input to the fail data register. The comparison circuit includes a first group of inputs coupled to outputs of a function circuit in the integrated circuit. The comparison circuit also includes a second group of inputs coupled to a source of expect data associated with normal function circuit performance. When a comparison between read data from the outputs of the function circuit and corresponding expect data indicates malfunction of the function circuit, data related to the malfunction are stored in the fail data register. A separate integrated circuit select line is coupled to each integrated circuit to allow transmission of the stored failure data without bus contention. As a result, many integrated circuits that are being tested may share an I/O bus, because the integrated circuits under test only output failure data on the I/O bus. Further, each integrated circuit only provides failure data to an external test data evaluation apparatus in response to selection signals from the external test data evaluation apparatus. The efficiency with which integrated circuits may be tested is thereby increased.