METHOD FOR IMPROVING THE SPEED OF BEHAVIORAL SYNTHESIS LINKS TO LOGIC SYNTHESIS

Behavioral synthesis allows a circuit design to be specified in a high-level hardware description language (HLHDL) that is more oriented towards expressing the desired behavior than the underlying hardware mechanisms by which such behavior will be accomplished. The present invention permits behavioral synthesis to be accomplished with control chaining information, but with the control chaining information determined by a basic data-flow based pretiming. Control chaining is useful because it permits advanced scheduling techniques in which the computation of a conditional functional unit can be considered for scheduling in the same clock cycle as the functional units that depend on the evaluation of that conditional functional unit. The present invention speeds up the step of pretiming, responsible for determining control chaining information, by eliminating additional processing, beyond data-flow chaining, for determining control chaining ready times. Additional control chaining procedures are eliminated in the pretiming step by adding the following two steps to the behavioral synthesis process: i) following the translation of the HLHDL into an RTL circuit description, but before the step of pretiming, the RTL circuit description is temporarily altered such that the functional units activated by each control signal (i.e., activation signal) are in the transitive fanout of their control signal; and ii) once pretiming has been accomplished, the circuit representation is reverted back to its original state. Other than these two additional steps, a known process for behavioral synthesis can be followed.