CONVULTION CODE GENERATOR AND DIGITAL SIGNAL PROCESSOR WHICH INCLUDES THE SAME

A convolution code generator according to the present invention simultaneously generates convolution codes with respect to input data word by word when a digital signal processor in which the convolution code generator can be installed has a bus configuration of a broad data width. The convolution code generator, which generates an (n, k, m) convolution code, wherein n is a code word length, k is a message block length, and m is a memory block, includes: a temporary data storing unit for temporarily storing input data of a word of a predetermined data width consisting of a plurality of bits, the temporary data storing unit including cells of a first group corresponding to a word and m−1 cells of a second group; and a plurality of exclusive logic operation units selectively connected to the cells of the first and second groups for generating the (n, k, m) convolution code with respect to input bits stored in the cells, wherein a part of data of a previous word is stored in the cells of the second group with respect to a present word stored in the cells of the first group. Also, according to the present invention, there is provided a digital signal processor including the convolution code generator.