VIRTUAL LOGIC SYSTEM FOR SOLVING SATISFIABILITY PROBLEMS USING RECONFIGURABLE HARDWARE

A virtual logic system for solving satisfiability problems on reconfigurable hardware, such that the reconfigurable hardware can be used to solve problems much larger than its available capacity. In an illustrative embodiment, a set of reconfigurable hardware including a number of field programmable gate arrays (FPGAs) is configured to solve a satisfiability problem. The satisfiability problem is decomposed into a number of independent and disjoint subproblems, e.g., using a simple decomposition in conjunction with disjoint partitioning, such that each of the subproblems is implementable within a given one of the FPGAs without the need for any inter-FPGA communication. Each FPGA then independently determines a satisfiability indication for one of the subproblems. At least a subset of the FPGAs may each be used to process more than one of the subproblems.