FAILURE ANALYZING METHOD AND APPARATUS

There is provided a failure analyzing apparatus and a failure analyzing method which are capable of automatically finding a failure address and the number of failures from a fail bit map obtained from the test result of an IC memory. The fail bit map is two-dimensional Wavelet-transformed, and the X directional high-pass and the Y directional low-pass information (the longitudinal component) XHL(i, j) of the two-dimensional Wavelet-transformed result is added up for each i in the Y direction to create a histogram. A failure address X is found from an address i having an added value other than zero, and the number of failures is found from the absolute value of the added value. In addition, the fail bit map is scanned in the Y direction for each of the failure addresses to output a Y address at which the map changes from a pass to a failure and a Y address at which the map changes from a failure to a pass as well as the number of failures between those two Y addresses.