MICROPROCESSOR CIRCUITS, SYSTEMS, AND METHODS WITH COMBINED ON-CHIP PIXEL AND NON-PIXEL CACHE STRUCTURE

A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.