IMAGE PROCESSING APPARATUS

An image processing apparatus which can effectively use a storage circuit provided together with a logic circuit, perform high speed processing, and reduce the power consumption without causing a decline in the performance. The image processing system includes a DRAM for storing image data and a logic circuit, which are provided together on a semiconductor chip. The DRAM is divided into a plurality of DRAM modules, and the divided plurality of DRAM modules are arranged around a logic circuit portion for carrying out graphic drawing processing etc. When the ratio of valid data occupying bit lines in one access increases, the distances from the DRAM modules to the logic circuit portion become uniform, the length of the longest path interconnection can be made shorter comparing with the case of arrangement fixed in one direction, and the overall operating speed can be improved.