FRAME ASSEMBLY IN DEQUEUING BLOCK

A multiport data communication system for switching data packets between ports comprising a plurality of receive ports for receiving data packets, a memory storing the received data packets, and a plurality of transmit ports each having a transmit queue. Logic circuitry for each transmit port controls reading from memory data corresponding to each data packet to be transmitted from the respective transmit port, reassembling the data read from the memory, and writing the reassembled data to the corresponding transmit queue. A monitoring circuit monitors the received data packets prior to storing them in the memory and determines whether a respective data packet should have the VLAN tag inserted/stripped/modified and/or the Device ID inserted/stripped. Reassembling the data includes inserting/stripping/modifying a VLAN tag and/or inserting/stripping a Device ID into the data read from the memory in accordance with a result of the determination of the monitoring circuit prior to writing the reassembled data into the corresponding transmit queue.